The invention disclosed broadly relates to the field of semi-conductor devices, and more particularly relates to the field of bipolar transistors.
Referring to FIG. 1, a conventional vertical npn (n-type emitter, p-type base, n-type collector) bipolar transistor 100, shown schematically, has a heavily doped buried subcollector (SC) 102 underneath the collector (C) 104. The subcollector layer 102 is quite thick, typically around 2000 nanometers (nm), to minimize collector series resistance. To ensure that the subcollector is effective in reducing collector series resistance, there is a collector reachthrough region 106 which provides a low-resistance connection between the subcollector layer 102 and the collector contact electrode 108 located at the top of the silicon surface. The collector reachthrough 106 is usually a heavily doped semiconductor region of the same type as the collector and subcollector. For the vertical npn transistor shown in FIG. 1, the n+reachthrough is also shown. The transistor 100 also comprises a base layer 110 located over the collector 104 and an emitter 112 located over the base 110. There is a space-charge region, also called a depletion region 114, associated with the p/n diode formed between the base 110 and the collector 104. In a typical bipolar transistor, this depletion region is formed mostly from the relatively lightly doped collector of the base-collector diode. Therefore, the collector 104 consists of the space-charge region 114 and the quasi-neutral region 118. The subcollector 102 is located on a p-type substrate 116.
Referring to FIG. 2, there is shown schematically a conventional npn bipolar transistor 200 built on an insulator 204. The transistor 200 comprises a substrate 202, an insulator 204, and an n+subcollector region 206 above the insulator 204. The collector 208 includes a depleted region 210 bordering the base 212. An emitter 214 is located above the p-type base 212. For some applications, it is desirable to build a vertical bipolar transistor on an insulator. However, the silicon layer on the insulator must be thick in order to accommodate the thick subcollector layer. Such thick-silicon Silicon-on-Insulator (SOI) technology is not compatible with SOI Complementary Metal-Oxide Silicon (CMOS) which employs thin-silicon SOI technology.
Referring to FIG. 3, there is shown a thin-silicon SOI vertical npn bipolar transistor 300 which is compatible with SOI CMOS. Such a structure is discussed in U.S. patent application Ser. No. 09/757,965, filed Jan. 10, 2001, T. H. Ning, xe2x80x9cSilicon-on-insulator (SOI) bipolar transistor useful alone or in SOI BiCMOS.xe2x80x9d Transistor 300 comprises a fully depleted collector 305, with no quasi-neutral collector region and no subcollector region directly underneath the base 306. After traversing the base layer 306, a minority carrier injected from the emitter 308 will drift more-or-less laterally towards a collector reachthrough 310. Thus the speed of this thin-SOI fully-depleted-collector transistor 300 depends on the length of the more-or-less lateral drift path. For a transistor designed using 250-nm rules, the drift-path length can be greater than 700 nm, severely limiting the transistor speed.
Power transistor designers have been using SOI technology to isolate one transistor from another. For example, a high-voltage npn bipolar transistor on a SOI substrate was described in the publication xe2x80x9cAnalysis of new high-voltage bipolar silicon-on-insulator transistor with fully depleted collector,xe2x80x9d by T. Arnborg and A. Litwin, in IEEE Trans. Elect. Dev., Vol. 42, No. 1, pp. 172-177, 1995. FIG. 4 shows a schematic of this prior art SOI bipolar device 400. As a power device, there is a large separation between the p-type base region 402 and the n+collector contact region 404 in order to be able to sustain a large reverse bias voltage between the base 402 and the collector contact 404.
The device characteristics of transistor 400 are influenced by the voltage applied to a back electrode 406 underneath the buried oxide 408. The transistor 400 also comprises a first oxide trench 410 on the collector side and a second oxide trench 412 on the emitter side. In particular, the back electrode 406 can be biased to cause majority carrier accumulation near the silicon-oxide interface. However, by not having a collector reachthrough (i.e., a heavily doped n+region connecting between the n+collector contact 404 at the silicon surface to the buried oxide surface 408) there is a high-resistance path between the majority carrier accumulation layer located at the bottom of the silicon layer and the n+collector contact 404 located at the top of the silicon layer. As a result, a majority carrier accumulation layer in this prior art does not function as an effective subcollector layer in substantially reducing the collector series resistance of the transistor. Without a low-resistance collector reachthrough, the prior art device is not suitable for building high-speed transistors, with or without a majority carrier accumulation layer in the collector part of the silicon layer. Therefore, there is a need for a bipolar transistor structure that overcomes the drawbacks of the prior art.
Briefly, according to the invention, an electronic circuit comprises a bipolar transistor that includes a conductive region serving as a back electrode, an insulator layer over the back electrode and a semiconductor layer of either an n-type or p-type material over the insulator layer. The semiconductor layer includes a doped region used as the collector and a heavily doped region used as a reachthrough between the insulator layer and the contact electrode to the collector. A majority carrier accumulation layer is induced in the collector by the application of a bias voltage (Vs) to the back electrode.